RS Flip-Flop Memory Lab
RS Flip-Flop Logic Lab
1-Bit Latch Memory Simulation (NAND Implementation)
S (Set)
R (Reset)
NAND
NAND
Q: 0
Q’: 1
STANDBY
| S | R | Q | State |
|---|---|---|---|
| 1 | 1 | Last | Latch |
| 0 | 1 | 1 | SET |
| 1 | 0 | 0 | RESET |
| 0 | 0 | 1* | Invalid |
*NAND Flip-flop is Active-Low. S=0 sets the output. 0-0 is a forbidden state as both Q and Q’ become HIGH.